1. Technical Field
The present invention relates to semiconductor package substrates, and more particularly, to first electrically connecting pads of a semiconductor package substrate for fine pitch application and enhanced bonding of semiconductor chips.
2. Description of Related Art
In flip-chip technology, electrode pads are formed on the IC semiconductor chip and an organic circuit board also has electrically connecting pads corresponding to the electrode pads in position. Solder structures or other conductive adhesive materials are formed between the electrode pads and the circuit boards for providing electrical and physical connections between the semiconductor chip and the circuit board. Related technology is disclosed in U.S. Pat. No. 6,809,262 (TW Patent No. 572361).
Referring to FIGS. 1A and 1B, a circuit layer 11 is formed on at least one surface of a substrate main body 10. The circuit layer 11 comprises a plurality of electrically connecting pads 110 and circuits 112, and portions of the circuits 112 are electrically connected with the electrically connecting pads 110 and thus electrically connected to the internal circuits (not shown in the drawings). Moreover, an insulative protective layer 13 is formed on the substrate main body 10, having an opening 130 for exposing the electrically connecting pads 110 and portions of the circuits 112, in which an solder layer 14 made of solder is formed on the exposed circuits 112 and electrically connecting pads 110, so as to avoid oxidation or provide an electrical connecting means for other electrical devices.
Referring to FIG. 2, a semiconductor chip 20 is mounted on the electrically connecting pads 110 in the opening 130 of the insulative protective layer 13. The semiconductor chip 20 has a plurality of electrode pads 21 each formed with a bump 22, allowing the bump 22 to be electrically connected to a solder layer 14 on each electrically connecting pad 110 correspondingly, so as to reduce the overall height of the package. Moreover the opening 130 is filled with an underfill 23, and since the aperture of the opening 130 is sufficiently large to expose a plurality of electrically connecting pads 110 and accommodate the underfill 23 without resulting in a flash incidence.
However, the electrically connecting pads 110 extend sideward to the circuits 112 as shown in FIG. 1A, preventing the bumps 22 of the semiconductor chip 20 from completely covering the electrically connecting pads 110 as shown in FIG. 2. Hence, a circuit-extending portion of the electrically connecting pads 110 is susceptible to concentration of stress, thus leading to cracking of the bumps 22 and poor bonding between the bumps 22 and the electrically connecting pads 110.
Moreover, a circuit 112 is formed between two adjacent electrically connecting pads 110, which lengthen the distance between the two adjacent electrically connecting pads 110. As the distance between two adjacent electrically connecting pads 110 cannot be reduced, fine pitch application is unavailable.
Thus, there is an urgent need to develop a semiconductor substrate in which the problem that the electrically connecting pads cannot be completely covered by the bumps of the semiconductor chips is solved, and the pitch distance between two electrically connecting pads can be reduced for fine pitch application.